For the present, virtually all mainstream electronic components and systems, such as microprocessors, are synchronous systems employing one or more system clocks that act as the driving force or “heart” of the electronic system. As a result, more often than not, it is critical that a given system clock signal arrive at various points in the system at virtually the same time. As discussed below, this situation can create a significant complication.
FIG. 1 shows a typical length of wire 100 including, from left to right, in the direction shown by arrow 102, points 101, 103 and 105.
As is well known, the physics of conductors and wave propagation dictate two important facts: first, the absolute speed limit for any signal moving from point 101 to points 103 or 105 is the speed of light; second, since wire 100 is typically a metallic conductor, with an inherent resistance, a signal propagating in wire 100 will actually travel at a speed significantly less than the speed of light.
As a result of these physical limitations on the speed at which a signal can propagate through wire 100, it follows that the greater the distance between two points on/in wire 100, the longer it takes the signal to reach the point. Consequently, a signal traveling from point 101, in the direction shown by arrow 102, will take less time to reach point 103, i.e., travel distance 107, than it will take to reach point 105, i.e., travel distance 107 and distance 109, and there is a time delay between when the signal reaches point 103 and when it reaches point 105. In addition, as can be seen from the discussion above, as long as wire 100 has a reasonably consistent composition and the wire lies on the same metal layer, the time delay is typically proportional to the distance traveled, i.e., twice the distance results in approximately twice the delay.
As mentioned above, in a typical microprocessor, a given system clock signal arrives at one or more pins located around the periphery of the microprocessor chip. In addition, there are typically numerous points, located at different distances from the periphery of the chip and the clock pins, which must receive the clock signal at the same time. Given the discussion above with respect to FIG. 1, it can be understood that the problem of ensuring a given clock signal received at a first point arrives, virtually simultaneously, at various other points, at various distances from the first point, and connected to the first point by differing length wires, such as wire 100, is significant.
The introduction of a time delay, also called simply a “delay”, between when one point receives a clock signal and when a second point, that should receive the clock signal at the same time, actually receives the clock signal is known as clock skew. Consequently, the ideal system has a zero clock skew, or at least a minimal clock skew. If clock skew becomes too large, the system, at a minimum, will operate inefficiently, typically slower with more errors. In addition, if the clock skew is more extreme, the system architecture will simply break down and the microprocessor will introduce so many errors that the system will fail.
As clock speeds become faster and faster, and more operations are required per clock, the problem of clock skew becomes even more pronounced and the margin for error is further reduced. However, this problem is not new and several mechanisms are in wide use in the art to reduce the clock skew problem including using multiple clock inputs, using multiple clock signals, and introducing delays between points to slow down the signal between close points so the more distant points receive the signal at the same time as the close points.
Virtually every mechanism in use today to minimize or eliminate clock skew requires that the time delay, between the arrival of a signal at two points, typically the clock input pin and another point within the chip, be known. In the prior art the method of calculating this time delay was to simply calculate the distance between the two points and then use this “raw” distance to estimate delay. One problem with these prior art methods was that they failed to take into account blockages between two points.
Blockages between two points in a microprocessor are typically created by the placement of circuit blocks, reserved channels and routing, pre-existing power and ground terminals, or one of several other microprocessor components, along the path between the two points. As noted above, in the prior art, the existence of these blockages was simply ignored and it was assumed there were no blockages.
In the prior art, the “raw” distance, i.e., the distance not taking into account blockages, between points was then used to determine delay. In the prior art, when a blockage did exist, it was simply routed around. However, in the prior art, the additional reroute distance was never used to re-calculate delay and therefore a certain amount of clock skew was almost guaranteed to be introduced using prior art methods. As noted above, as microprocessor speeds continue to increase to the 3 and 4 gigahertz level, it is becoming imperative that clock skew be absolutely minimized or eliminated, to ensure proper microprocessor function.
What is needed is a more accurate and realistic method for calculating delay between two points in microprocessors.